`timescale 1ns / 10ps
module single_bit_test;

	reg a_in, b_in, c_in;
	reg rst_in;
	wire s_out, c_out;

	single_bit_full_adder sbfa (.a(a_in), .b(b_in), .c(c_in), .rst(rst_in), .s(s_out), .cout(c_out));

	initial begin
		integer i;
		integer preamb, period;

		$dumpfile("sbfa.vcd");
		$dumpvars(0, single_bit_test);
		
		{a_in, b_in, c_in, rst_in} <= 0;


		for (i = 0; i < 8; i+=1) begin
			preamb = $urandom_range(0, 5);
			period = $urandom_range(0, 5);

			#(preamb);
		 	$monitor("A=0x%0h B=0x%0h Cin=0x%h Sout=0x%h Cout=0x%h @ t=%3d", a_in, b_in, c_in, s_out, c_out, $time);
			{a_in, b_in, c_in} <= i;
			#(period);
		 	$monitor("rst set @ t=%3d", $time);
			rst_in <= 1;
			#(10 - preamb - period);
		 	$monitor("rst reset @ t=%3d", $time);
			rst_in <= 0;
		end
		#10 $monitor("DONE");

	end

endmodule
